Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
Market pressures continually drive semiconductor manufacturers to reduce the size of die packages to fit within the space constraints of electronic devices, while concurrently increasing the functional capacity of each package to meet operating parameters. One approach for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the package's “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically-stacked packages can be electrically and thermally interconnected by arrays of pillars. A common approach to forming these pillars includes forming a photoresist pattern that masks portions of the die surface other than portions at which the pillars are to be formed. After the photoresist pattern is formed, metal is electrochemically plated onto the unmasked portion of the die surface. Finally, the photoresist around the newly formed pillars is removed.
A challenge associated with electrochemical plating of metal onto pillars in semiconductor die assemblies is that, in practice, the plated metal tends to be non-uniform in height among pillars throughout a given die and/or among pillars throughout a given wafer. These non-uniformities can complicate forming reliable electrical and thermal connections between neighboring dies. For example, when neighboring dies in a semiconductor die assembly are brought together during manufacturing, gaps between pillars on one of the dies and corresponding bond pads on the neighboring die may vary considerably when the pillars have variable heights and the bond pads are coplanar. In the context of electrical-interconnect pillars, when a pillar-to-bond-pad gap is too large to be bridged by solder, an entire package may inoperative and need to be scrapped. Similarly, in the context of thermal pillars, when a pillar-to-bond-pad gap is excessively large, the rate at which heat is dissipated from semiconductor dies in the package may be unacceptably low.